Photoresist patterning is a key step in the formation of integrated circuits in semiconductor devices. A photoresist layer is typically spin coated on a substrate and patternwise exposed by employing an exposure tool and a mask that contains a device pattern. The mask may be comprised of an opaque material such as chrome on a transparent substrate like quartz. Other masks called phase shifting masks have regions that transmit light which is 180° out of phase with light transmitted through an adjacent region. Radiation is transmitted through a mask to selectively expose portions of the photoresist layer which are later developed in a media such as an aqueous base solution to produce a photoresist pattern. For a positive tone photoresist layer, exposed portions are removed while unexposed portions remain on the substrate. With a negative tone photoresist, exposed portions are typically crosslinked and remain on the substrate while unexposed portions are washed away by the developer.
Each technology generation or node in the microelectronics industry is associated with a particular minimum feature size in the photoresist pattern. As technology advances have been continuous in recent years, the minimum feature size requirement has rapidly shifted from 250 nm to 180 nm and then to 130 nm. New photoresists, masks, and exposure tools are now being implemented for 100 nm and sub-100 nm technology nodes.
An important aspect of the photoresist patterning process is the accurate placement of a second layer pattern on a first pattern that formed in a substrate. For example, in a damascene process, trenches formed in a second photoresist layer are overlaid on vias in a first pattern that has been etched into a dielectric layer. As new technology nodes are introduced, the overlay specification for printing a second layer pattern over a first pattern has been tightened to 65 nm or even less in some cases. There are two major factors contributing to this overlay error which is also called layer to layer error. One is optical projection system error and the other is mask to mask error.
In the current practice of evaluating mask to mask error, reference marks are typically placed on a mask outside the pattern and the forbidden area. As shown in FIG. 1, a conventional mask 1 has a pattern area 2 comprised of opaque and transparent regions in a center location which is surrounded by a forbidden area 3 and is used to form a first pattern in a substrate. The outer region 4 of the mask 1 has opaque or transparent reference marks 5a–5f that are not printed during a patterning process. Similarly, a second mask (not shown) which is used to print a second layer pattern has a matching set of reference marks located in an outer region that are at similar (x,y) coordinates to the reference marks 5a–5f on the mask 1. A metrology tool is used to obtain mask to mask overlay without involving photoresist exposures. Thus, the position of each of the reference marks 5a–5f on the mask 1 and the position of the reference marks on the second mask are measured and an offset in terms of an overlay error in the x-direction and in the y-direction is calculated for each matched pair of reference marks. The offset data is used to make a correction in exposure tool settings when using the mask 1 and the second mask in subsequent patterning steps so that the overlay of a second layer pattern on a first pattern is optimized.
The resulting mask to mask error map depicted in FIG. 2 is simplified compared to actual practice but indicates that the same correction is applied to all areas of the mask in region 6 including the device pattern area 2 based on the offset of marks 5a, 5b to the matching reference marks on the second mask. Likewise, only one correction is made for all areas of the mask in region 7 based on measurements of reference marks 5c, 5d and the matching reference marks on the second mask and only one correction is made in region 8 based on the measurements of marks 5e, 5f and the matching reference marks on the second mask. For advanced technologies that are approaching nodes of 100 nm or less, the location of reference marks outside the device pattern does not provide a second layer pattern to first layer pattern overlay accuracy that satisfies current overlay specifications. Therefore, a new method is needed that enables alignment to within about 45 nm of a targeted position.
In U.S. Pat. No. 5,044,750, a method is mentioned for checking alignment of a pattern in a photoresist layer. Geometric patterns in a diamond shape are added to a mask in a progressively overlapping edge to edge orientation with increments of 0.05 microns in distance between the ends of the diamonds. The diamond shapes can be oriented in both x and y directions in order to provide full (x,y) dimension accuracy.
U.S. Pat. No. 6,352,323 provides a method of aligning a mask level to marks in two previous layers. An algorithm with weighting factors is applied to determine overlay offsets in x and y directions.
An in-situ overlay method is described in U.S. Pat. No. 4,929,083. A key step is to monitor the output signal generated by a photodetector in response to light angularly radiated by one or more test patterns on a reusable calibration wafer while the test pattern is being exposed to an aerial image of a matching calibration mask. This process seems best suited for setting up a tool for manufacturing. During actual production, mask to mask error would still have to be evaluated for fine corrections.
In U.S. Pat. No. 6,288,556, electrical resistance is measured to determine the amount of misregistration between two patterned levels. Electrical resistance is measured between terminals provided in first and second level patterns that have been etched into a substrate. A current is applied between two terminals and voltage is monitored between two different terminals in a pattern.